Effective Memory Access Time
Blend cache-hit and miss-penalty times into the average access time your CPU actually sees.
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The engineering
Average Memory Access Time (AMAT) collapses a two-tier cache/memory pair into a single expected latency: you always pay the hit time, and on the fraction of accesses that miss you also eat the miss penalty. Reach for it when weighing whether a bigger cache, faster fill, or lower miss rate buys you more.
The lever is almost always miss rate, because the penalty is huge relative to the hit. A 1 ns cache with a 100 ns DRAM penalty at 5% misses averages 6 ns — six times the hit time. Cutting the miss rate to 2% drops AMAT to 3 ns; shaving the hit time barely moves the needle. For multilevel hierarchies, recurse: the L1 miss penalty is itself the L2 AMAT.
Where this math comes from
The idea of an averaged access time follows directly from Maurice Wilkes's 1965 proposal for a 'slave memory' — the first cache — which only pays off if most references hit it. Once caches were real, designers needed a scalar to compare designs, and the hit-time-plus-miss-cost expression became the standard back-of-envelope.
John Hennessy and David Patterson canonized AMAT in Computer Architecture: A Quantitative Approach (1990), turning it into the workhorse formula every architecture student now derives, complete with the multilevel recursion for L1/L2/L3 hierarchies.
- 1965Maurice WilkesProposes the 'slave memory' — the concept of a cache.
- 1968IBM System/360 Model 85First commercial machine to ship a hardware cache.
- 1990Hennessy & PattersonFormalize AMAT and its multilevel form in their architecture text.
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